The present invention relates to a semiconductor integrated circuit device. More particularly, the invention relates to a power supply technology for supplying power to that region (the power cut-off region) of such a semiconductor integrated circuit device to which the supply of power is cut off as needed.
As described in Japanese Unexamined Patent Publication No. 2006-49477 (Patent Literature 1 hereunder), there exist semiconductor integrated circuit devices each having a semiconductor chip joined by flip-chip bonding to a wiring substrate (package substrate).
A power cut-off technique is one of the power-saving techniques applicable to the semiconductor integrated circuit device. The power cut-off technique involves dividing the interior of the semiconductor integrated circuit device into a plurality of circuit blocks so that the power to any inactive circuit block may be cut off, thereby suppressing leak currents that contribute to power dissipation. Japanese Unexamined Patent Publication No. 2010-226083 (Patent Literature 2 hereunder) and Japanese Unexamined Patent Publication No. 2009-200690 (Patent Literature 3 hereunder), among others, describe the power cut-ff technique. The technique disclosed in Patent Literature 2 involves allowing a power cut-off technique utilizing a power cut-off switch arrangement and a power-saving technique based on DVFS (Dynamic Voltage Frequency Scaling) to coexist so as to reduce power dissipation efficiently. Patent Literature 3 proposes a method for designing a semiconductor integrated circuit with a minimum of through-current countermeasures taken while aiming at reducing power dissipation.